Second Generation of Power Interlock Controller (PICv2)

In order to meet the dependability objectives of the HL-LHC era, TE- MPE-MI needs to develop a second generation Powering Interlock Controller (PIC), which will both address architectural improvements and modifications of the LHC and HL-LHC magnet protection systems as well as guarantee the current dependability and maintainability of the magnet interlock system for the lifetime of the HL-LHC project.

Reference Documents

TITLE REFERENCE LAST UPDATE STATUS
Project Proposal PIC V1.0 (Roadmap) ACC-PM-RM-0006 v.1 2016-02-18 Cancelled
Project Proposal PIC V2.0 (Roadmap) ACC-PM-RM-0006 v.2 2021-04-22 Engineering Check
Reaction time Study of a full industrial version of the PIC PIC Reaction Time 2021-04-04 Released
Underground integration list 3D Model - new HL-LHC galleries 2022-10-04 Released
Interface Specification: Splitting and Thermoswitch Modules of the DFHX and DFHM of the SC Link Systems DFH - Interface Specification 2022-09-15 DRAFT
INNER TRIPLET INTERLOCK PANEL INNER TRIPLET INTERLOCK PANEL 2023-09-29 RELEASED
EPC/CCE HL-LHC Inner Triplet Interlock Panel Technical Presentation 2022-10-28 OBSOLETE
WP7 - Relocation of the Powering Interlock Controllers outside of the RRs LHC-CIP-EC-0007 2024-07-02 Released

Quality Assurance - Convention

TITLE REFERENCE LAST UPDATE STATUS
Equipment Naming Conventions LHC-PM-QA-204 2006-05-24 RELEASED
Naming of Electrical Circuits and Power Converters for: LHC Injection Lines, CNGS AB-PC-QA-0001 2007-02-26 RELEASED
Description of QPS Signals in LHC LHC-DQ-ES-0003 2005-09-28 RELEASED
Basic Syntactic Rules for Naming of LHC Entities and their Parameters for the CERN Control Centre LHC-C-QA-0001 2004-07-26 RELEASED
Naming of LHC Entities and their Parameters for the CERN Control Centre LHC-C-QA-0002 2004-07-26 RELEASED

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