Introduction

The first PICv2 prototype was developed to address the long-term obsolescence of the current PIC while significantly reducing the reaction time required for HL-LHC operation. At that stage of the project, the PIC was expected to interface directly with the PDSUs supervising the CLIQ units. In the event of a spurious CLIQ discharge, the beam had to be dumped within 470 μs, leaving approximately 80 μs for the PIC to detect the event and request a beam dump.

To meet these requirements, the prototype investigated a fully industrial solution while preserving the proven hardware architecture of the operational PIC. The main objectives were:

• Replace the obsolete Siemens S7-300 PLC family with the modern Siemens S7-1500 platform.
• Develop the QPS and Power Converter interfaces using industrial optocouplers.
• Introduce redundant industrial power supplies.
• Replace the obsolete CPLD beam-dump logic with a high-performance B&R PLC featuring a 1 μs reaction technology.

Concept

The prototype architecture was based entirely on PLC technology.

A master crate (CIPM) houses two Siemens S7-1500 CPUs connected to remote I/O stations through two independent PROFINET networks. The primary CPU executes the complete PIC application, while the secondary CPU is dedicated exclusively to the beam-dump function, providing an independent protection path.

Only two types of remote I/O crates are required to interface all LHC powering subsectors:

• CIP2SA – Main interface crate
• CIP2SB – Extended interface crate

These are complemented by:

• CIP2S, providing redundant 24 VDC power supplies;
• CIP2ST, collecting the thermal-switch signals from the DFHX and DFHM cryogenic systems for HL-LHC Points 1 and 5.

All crates are based on standard 6U, 19-inch SCHROFF chassis. The CIPSA and CIPSB crates each contain two redundant Siemens ET200MP remote I/O stations connected, via a custom backplane and flat cables, to removable interface boards carrying the field electronics.

Control Architecture

Lessons Learned

The prototype proved invaluable in validating the feasibility of the proposed architecture and identifying several critical design risks before series production.

The design of the PIC interfaces is driven by two fundamental constraints:

• Latency: the complete hardware interlock chain must satisfy the required reaction time.
• Electrical compatibility: all interfaces must comply with the existing current-loop specification used between the Quench Protection System (QPS), Power Converter (PC), the energy extraction (EE) and PIC systems:
  • 10 mA < I < 20 mA
  • Maximum voltage drop: 2.5 V per connected system

Initially, the development effort focused primarily on achieving the required latency. Several industrial optocouplers with excellent switching performance were evaluated and integrated into prototype interface boards. However, electrical measurements revealed that their integrated protection circuitry introduced a voltage drop of approximately 7 V, making them incompatible with the existing current-loop specification.

Following an extensive evaluation of alternative devices, a suitable industrial optocoupler satisfying both the timing and electrical requirements was eventually identified, allowing the prototype to be completed and successfully deployed on the IT String.

Although technically successful, this work exposed a major long-term reliability concern: only a single manufacturer was found to supply optocouplers meeting all the required specifications. Such a dependency was considered unacceptable for a machine protection system expected to remain operational for decades, as it would simply replace one obsolescence issue with another.

This finding ultimately led to the abandonment of the fully industrial interface concept. The final PICv2 design instead adopts custom interface electronics using standard, widely available optocouplers, providing equivalent functional performance while ensuring long-term component availability and maintainability.

During the project, the machine protection architecture also evolved. The CLIQ protection strategy was modified so that the CLIQ QPS is connected directly to the Beam Interlock System (BIS), providing the required deterministic beam-dump path independently of the PIC. Consequently, the dedicated B&R beam-dump PLC investigated in the prototype was no longer required and does not form part of the final PICv2 architecture.